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? 2003 microchip technology inc. ds11195c-page 1 m mcp41xxx/42xxx features ? 256 taps for each potentiometer ? potentiometer values for 10 k ? , 50 k ? and 100 k ? ? single and dual versions ? spi? serial interface (mode 0,0 and 1,1) ? 1 lsb max inl & dnl ? low power cmos technology ? 1 a maximum supply current in static operation ? multiple devices can be daisy-chained together (mcp42xxx only) ? shutdown feature open circuits of all resistors for maximum power savings ? hardware shutdown pin available on mcp42xxx only ? single supply operation (2.7v - 5.5v) ? industrial temperature range: -40c to +85c ? extended temperature range: -40c to +125c block diagram description the mcp41xxx and mcp4 2xxx devices are 256- position, digital potentiometers available in 10 k ? , 50 k ? and 100 k ? resistance versions. the mcp41xxx is a single-channel device and is offered in an 8-pin pdip or soic package. the mcp42xxx con- tains two independent channels in a 14-pin pdip, soic or tssop package. the wiper position of the mcp41xxx/42xxx varies linear ly and is co ntrolled via an industry-standard spi interface. the devices con- sume <1 a during static operation. a software shut- down feature is provided that disconnects the ?a? terminal from the resistor stack and simultaneously con- nects the wiper to the ?b? te rminal. in addition, the dual mcp42xxx has a shdn pin that performs the same function in hardware. during shutdown mode, the con- tents of the wiper register can be changed and the potentiometer returns from shutdown to the new value. the wiper is reset to the mid-scale position (80h) upon power-up. the rs (reset) pin implements a hardware reset and also returns th e wiper to mid-scale. the mcp42xxx spi interface incl udes both the si and so pins, allowing daisy-chaining of multiple devices. chan- nel-to-channel resistance matching on the mcp42xxx varies by less than 1%. these devices operate from a single 2.7 - 5.5v supply and are specified over the extended and industrial temperature ranges. package types 16-bit shift v dd v ss si sck rs shdn pb1 pa1 pw1 resistor array 1 * wiper register pb0 pw0 pa0 resistor array 0 wiper register register s0 control logic cs * potentiometer p1 is only available on the dual mcp42xxx version. mcp42xxx 1 2 3 4 11 12 13 14 8 9 10 5 6 7 pdip/soic/tssop pb1 pa1 pw1 shdn so rs pw0 pb0 cs pa0 sck si v ss v dd mcp41xxx 1 2 3 4 5 6 7 8 pdip/soic pb0 pa0 v dd pw0 v ss cs sck si single/dual digital potentiometer with spi ? interface
mcp41xxx/42xxx ds11195c-page 2 ? 2003 microchip technology inc. 1.0 electrical characteristics dc characteristics: 10 k ? version electrical characteristics: unless otherwise indicated, v dd = +2.7v to 5.5v, t a = -40c to +85c (tssop devices are only specified at +25c and +85c). typical specifications represent values for v dd = 5v, v ss = 0v, v b = 0v, t a = +25c. parameters sym min typ max units conditions rheostat mode nominal resistance r 8 10 12 k ? t a = +25c (note 1) rheostat differential non linearity r-dnl -1 1/4 +1 lsb note 2 rheostat integral non linearity r-inl -1 1/4 +1 lsb note 2 rheostat tempco ? r ab / ? t ? 800 ? ppm/c wiper resistance r w ? 52 100 ? v dd = 5.5v, i w = 1 ma, code 00h r w ? 73 125 ? v dd = 2.7v, i w = 1 ma, code 00h wiper current i w -1 ? +1 ma nominal resistance match ? r/r ? 0.2 1 % mcp42010 only , p0 to p1; t a = +25c potentiometer divider resolution n 8 ? ? bits monotonicity n 8 ? ? bits differential non-linearity dnl -1 1/4 +1 lsb note 3 integral non-linearity inl -1 1/4 +1 lsb note 3 voltage divider tempco ? v w / ? t ? 1 ? ppm/c code 80h full scale error v wfse -2 -0.7 0 lsb code ffh, v dd = 5v, see figure 2-25 v wfse -2 -0.7 0 lsb code ffh, v dd = 3v, see figure 2-25 zero scale error v wzse 0 +0.7 +2 lsb code 00h, v dd = 5v, see figure 2-25 v wzse 0 +0.7 +2 lsb code 00h, v dd = 3v, see figure 2-25 resistor terminals voltage range v a,b,w 0?v dd note 4 capacitance (c a or c b ) ? 15 ? pf f = 1 mhz, code = 80h, see figure 2-30 capacitance c w ? 5.6 ? pf f = 1 mhz, code = 80h, see figure 2-30 dynamic characteristics (all dynamic characteristics use v dd = 5v) bandwidth -3db bw ? 1 ? mhz v b = 0v, measured at code 80h, output load = 30 p f settling time t s ?2?sv a = v dd ,v b = 0v, 1% error band, transition from code 00h to code 80h, output load = 30 pf resistor noise voltage e nwb ?9?nv/ hz v a = open, code 80h , f =1 khz crosstalk c t ?-95?dbv a = v dd , v b = 0v (note 5) digital inputs/outputs (cs , sck, si, so) see figure 2-12 for rs and shdn pin operation schmitt trigger high-level input voltage v ih 0.7v dd ??v schmitt trigger low-level input voltage v il ? ? 0.3v dd v hysteresis of schmitt trigger inputs v hys ?0.05v dd ? low-level output voltage v ol ? ? 0.40 v i ol = 2.1 ma, v dd = 5v high-level output voltage v oh v dd - 0.5 ? ? v i oh = -400 a, v dd = 5v input leakage current i li -1 ? +1 a cs = v dd , v in = v ss or v dd , includes v a shdn =0 pin capacitance (all inputs/outputs) c in , c out ?10?pfv dd = 5.0v, t a = +25c, f c = 1 mhz power requirements operating voltage range v dd 2.7 ? 5.5 v supply current, active i dda ? 340 500 a v dd = 5.5v, cs = v ss , f sck = 10 mhz, so = open, code ffh (note 6) supply current, static i dds ?0.01 1 acs , shdn , rs = v dd = 5.5v, so = open (note 6) power supply sensitivity pss ? 0.0015 0.0035 %/% v dd = 4.5v - 5.5v, v a = 4.5v, code 80h pss ? 0.0015 0.0035 %/% v dd = 2.7v - 3.3v, v a = 2.7v, code 80h note 1: v ab = v dd , no connection on wiper. 2: rheostat position non-linearity r-inl is the deviation from an ideal value measured between the maximum resistance and the mini mum resistance wiper positions. r-dnl measures the relative st ep change from the ideal between successive tap positions. i w = 50 a for v dd = 3v and i w = 400 a for v dd = 5v for 10 k ? version. see figure 2-26 for test circuit. 3: inl and dnl are measured at v w with the device configured in the voltage divider or potentiometer mode. v a = v dd and v b = 0v. dnl specification limits of 1 lsb max are specified monotoni c operating conditions. see figure 2-25 for test circuit. 4: resistor terminals a,b and w have no restrictions on polarity with respect to each other. full-scale and zero-scale error were measured using figure 2-25. 5: measured at v w pin where the voltage on the adjacent v w pin is swinging full-scale. 6: supply current is independent of current through the potentiometers.
? 2003 microchip technology inc. ds11195c-page 3 mcp41xxx/42xxx dc characteristics: 50 k ? version electrical characteristics: unless otherwise indicated, v dd = +2.7v to 5.5v, t a = -40c to +85c (tssop devices are only specified at +25c and +85c). typical specifications represent values for v dd = 5v, v ss = 0v, v b = 0v, t a = +25c. parameters sym min typ max units conditions rheostat mode nominal resistance r 35 50 65 k ? t a = +25c (note 1) rheostat differential non-linearity r-dnl -1 1/4 +1 lsb note 2 rheostat integral non-linearity r-inl -1 1/4 +1 lsb note 2 rheostat tempco ? r ab / ? t ? 800 ? ppm/c wiper resistance r w ? 125 175 ? v dd = 5.5v, i w = 1 ma, code 00h r w ? 175 250 ? v dd = 2.7v, i w = 1 ma, code 00h wiper current i w -1 ? +1 ma nominal resistance match ? r/r ? 0.2 1 % mcp42050 only , p0 to p1;t a = +25c potentiometer divider resolution n 8 ? ? bits monotonicity n 8 ? ? bits differential non-linearity dnl -1 1/4 +1 lsb note 3 integral non-linearity inl -1 1/4 +1 lsb note 3 voltage divider tempco ? v w / ? t ? 1 ? ppm/c code 80h full-scale error v wfse -1 -0.25 0 lsb code ffh, v dd = 5v, see figure 2-25 v wfse -1 -0.35 0 lsb code ffh, v dd = 3v, see figure 2-25 zero-scale error v wzse 0 +0.25 +1 lsb code 00h, v dd = 5v, see figure 2-25 v wzse 0 +0.35 +1 lsb code 00h, v dd = 3v, see figure 2-25 resistor terminals voltage range v a,b,w 0?v dd note 4 capacitance (c a or c b ) ? 11 ? pf f =1 mhz, code = 80h, see figure 2-30 capacitance c w ? 5.6 ? pf f =1 mhz, code = 80h, see figure 2-30 dynamic characteristics (all dynamic characteristics use v dd = 5v) bandwidth -3db bw ? 280 ? mhz v b = 0v, measured at code 80h, output load = 30 p f settling time t s ?8?sv a = v dd ,v b = 0v, 1% error band, transition from code 00h to code 80h, output load = 30 pf resistor noise voltage e nwb ?20?nv/ hz v a = open, code 80h , f =1 khz crosstalk c t ?-95?dbv a = v dd , v b = 0v (note 5) digital inputs/outputs (cs , sck, si, so) see figure 2-12 for rs and shdn pin operation. schmitt trigger high-level input voltage v ih 0.7v dd ??v schmitt trigger low-level input voltage v il ? ? 0.3v dd v hysteresis of schmitt trigger inputs v hys ?0.05v dd ? low-level output voltage v ol ? ? 0.40 v i ol = 2.1 ma, v dd = 5v high-level output voltage v oh v dd - 0.5 ? ? v i oh = -400 a, v dd = 5v input leakage current i li -1 ? +1 a cs = v dd , v in = v ss or v dd , includes v a shdn =0 pin capacitance (all inputs/outputs) c in , c out ?10?pfv dd = 5.0v, t a = +25c, f c = 1 mhz power requirements operating voltage range v dd 2.7 ? 5.5 v supply current, active i dda ? 340 500 a v dd = 5.5v, cs = v ss , f sck = 10 mhz, so = open, code ffh (note 6) supply current, static i dds ?0.01 1 acs , shdn , rs = v dd = 5.5v, so = open (note 6) power supply sensitivity pss ? 0.0015 0.0035 %/% v dd = 4.5v - 5.5v, v a = 4.5v, code 80h pss ? 0.0015 0.0035 %/% v dd = 2.7v - 3.3v, v a = 2.7v, code 80h note 1: v ab = v dd , no connection on wiper. 2: rheostat position non-linearity r-inl is the deviation from an ideal value measured between the maximum resistance and the mini mum resistance wiper positions. r-dnl measures the relative st ep change from the ideal between successive tap positions. i w = v dd /r for +3v or +5v for 50 k ? version. see figure 2-26 for test circuit. 3: inl and dnl are measured at v w with the device configured in the voltage divider or potentiometer mode. v a = v dd and v b = 0v. dnl specification limits of 1 lsb max are specified monotoni c operating conditions. see figure 2-25 for test circuit. 4: resistor terminals a,b and w have no restrictions on polarity with respect to each other. full-scale and zero-scale error were measured using figure 2-25. 5: measured at v w pin where the voltage on the adjacent v w pin is swinging full scale. 6: supply current is independent of current through the potentiometers.
mcp41xxx/42xxx ds11195c-page 4 ? 2003 microchip technology inc. dc characteristics: 100 k ? version electrical characteristics: unless otherwise indicated, v dd = +2.7v to 5.5v, t a = -40c to +85c (tssop devices are only specified at +25c and +85c). typical specifications represent values for v dd = 5v, v ss = 0v, v b = 0v, t a = +25c. parameters sym min typ max units conditions rheostat mode nominal resistance r 70 100 130 k ? t a = +25c (note 1) rheostat differential non-linearity r-dnl -1 1/4 +1 lsb note 2 rheostat integral non-linearity r-inl -1 1/4 +1 lsb note 2 rheostat tempco ? r ab / ? t ? 800 ? ppm/c wiper resistance r w ? 125 175 ? v dd = 5.5v, i w = 1 ma, code 00h r w ? 175 250 ? v dd = 2.7v, i w = 1 ma, code 00h wiper current i w -1 ? +1 ma nominal resistance match ? r/r ? 0.2 1 % mcp42010 only, p0 to p1;t a = +25c potentiometer divider resolution n 8 ? ? bits monotonicity n 8 ? ? bits differential non-linearity dnl -1 1/4 +1 lsb note 3 integral non-linearity inl -1 1/4 +1 lsb note 3 voltage divider tempco ? v w / ? t ? 1 ? ppm/c code 80h full-scale error v wfse -1 -0.25 0 lsb code ffh, v dd = 5v, see figure 2-25 v wfse -1 -0.35 0 lsb code ffh, v dd = 3v, see figure 2-25 zero-scale error v wzse 0 +0.25 +1 lsb code 00h, v dd = 5v, see figure 2-25 v wzse 0 +0.35 +1 lsb code 00h, v dd = 3v, see figure 2-25 resistor terminals voltage range v a,b,w 0?v dd note 4 capacitance (c a or c b ) ? 11 ? pf f =1 mhz, code = 80h, see figure 2-30 capacitance c w ? 5.6 ? pf f =1 mhz, code = 80h, see figure 2-30 dynamic characteristics (all dynamic characteristics use v dd = 5v.) bandwidth -3db bw ? 145 ? mhz v b = 0v, measured at code 80h, output load = 30 p f settling time t s ?18?sv a = v dd ,v b = 0v, 1% error band, transition from code 00h to code 80h, output load = 30 pf resistor noise voltage e nwb ?29?nv/ hz v a = open, code 80h , f =1 khz crosstalk c t ?-95?dbv a = v dd , v b = 0v (note 5) digital inputs/outputs (cs , sck, si, so) see figure 2-12 for rs and shdn pin operation. schmitt trigger high-level input voltage v ih 0.7v dd ??v schmitt trigger low-level input voltage v il ? ? 0.3v dd v hysteresis of schmitt trigger inputs v hys ?0.05v dd ? low-level output voltage v ol ? ? 0.40 v i ol = 2.1 ma, v dd = 5v high-level output voltage v oh v dd - 0.5 ? ? v i oh = -400 a, v dd = 5v input leakage current i li -1 ? +1 a cs = v dd , v in = v ss or v dd , includes v a shdn =0 pin capacitance (all inputs/outputs) c in , c out ?10?pfv dd = 5.0v, t a = +25c, f c = 1 mhz power requirements operating voltage range v dd 2.7 ? 5.5 v supply current, active i dda ? 340 500 a v dd = 5.5v, cs = v ss , f sck = 10 mhz, so = open, code ffh (note 6) supply current, static i dds ?0.01 1 acs , shdn , rs = v dd = 5.5v, so = open (note 6) power supply sensitivity pss ? 0.0015 0.0035 %/% v dd = 4.5v - 5.5v, v a = 4.5v, code 80h pss ? 0.0015 0.0035 %/% v dd = 2.7v - 3.3v, v a = 2.7v, code 80h note 1: v ab = v dd , no connection on wiper. 2: rheostat position non-linearity r-inl is the deviation from an ideal value measured between the maximum resistance and the mini mum resistance wiper positions. r-dnl measures the relative st ep change from the ideal between successive tap positions. i w = 50 a for v dd = 3v and i w = 400 a for v dd = 5v for 10 k ? version. see figure 2-26 for test circuit. 3: inl and dnl are measured at v w with the device configured in the voltage divider or potentiometer mode. v a = v dd and v b = 0v. dnl specification limits of 1 lsb max are specified monotoni c operating conditions. see figure 2-25 for test circuit. 4: resistor terminals a,b and w have no restrictions on polarity with respect to each other. full-scale and zero-scale error were measured using figure 2-25. 5: measured at v w pin where the voltage on the adjacent v w pin is swinging full-scale. 6: supply current is independent of current through the potentiometers.
? 2003 microchip technology inc. ds11195c-page 5 mcp41xxx/42xxx absolute maximum ratings ? v dd ...................................................................................7.0v all inputs and outputs w.r.t. v ss ............... -0.6v to v dd +1.0v storage temperature .....................................-60c to +150c ambient temp. with power applied ................-60c to +125c esd protection on all pins .................................................. 2kv ? notice: stresses above those listed under ?maximum rat- ings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specif ication is not implied. expo- sure to maximum rating conditions for extended periods may affect device reliability. ac timing characteristics electrical characteristics: unless otherwise indicated, v dd = +2.7v to 5.5v, t a = -40c to +85c. parameter sym min. typ. max. units conditions clock frequency f clk ??10mhzv dd = 5v (note 1) clock high time t hi 40 ? ? ns clock low time t lo 40 ? ? ns cs fall to first rising clk edge t cssr 40 ? ? ns data input setup time t su 40 ? ? ns data input hold time t hd 10 ? ? ns sck fall to so valid propagation delay t do ?80 nsc l = 30 pf (note 2) sck rise to cs rise hold time t chs 30 ? ? ns sck rise to cs fall delay t cs0 10 ? ? ns cs rise to clk rise hold t cs1 100 ? ? ns cs high time t csh 40 ? ? ns reset pulse width t rs 150 ? ? ns note 2 rs rising to cs falling delay time t rscs 150 ? ? ns note 2 cs rising to rs or shdn falling delay time t se 40 ? ? ns note 3 cs low time t csl 100 ? ? ns note 3 shutdown pulse width t sh 150 ? ? ns note 3 note 1: when using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation d elay time (t do ) and data input setup time (t su ). max. clock frequency is therefore ~ 5.8 mhz based on sck rise and fall times of 5 ns, t hi = 40 ns, t do = 80 ns and t su = 40 ns. 2: applies only to the mcp42xxx devices. 3: applies only when using hardware pins to exit software shutdown mode, mcp42xxx only.
mcp41xxx/42xxx ds11195c-page 6 ? 2003 microchip technology inc. figure 1-1: detailed serial interface timing. figure 1-2: reset timing. figure 1-3: software shutdown exit timing. cs sck si msb in t su t hd t cssr t csh t hi t lo t cso so t cs1 1/f clk t chs t do (first 16 bits out are always zeros) v out 1% 1% error band t s rs t s v out 1% t rs 1% error band cs t rscs code 80h is latched on rising edge of rs wiper position is changed to mid-scale (80h) if rs is held low for 150 ns cs t csl rs shdn t sh t rs t se t se
? 2003 microchip technology inc. ds11195c-page 7 mcp41xxx/42xxx 2.0 typical performance curves note: unless otherwise indicated, curve represents 10 k ? , 50 k ? and 100 k ? devices, v dd = 5v, v ss = 0v, t a = +25c, v b = 0v. figure 2-1: normalized wiper to end terminal resistance vs. code. figure 2-2: potentiometer inl error vs. code. figure 2-3: potentiometer mode tempco vs. code. figure 2-4: nominal resistance 10 k ? vs. temperature. figure 2-5: nominal resistance 50 k ? vs. temperature. figure 2-6: nominal resistance 100 k ? vs. temperature. note: the graphs and tables provided fo llowing this note are a statistical su mmary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or t ables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outside the warranted range. 0 0.2 0.4 0.6 0.8 1 0 32 64 96 128 160 192 224 256 code (decimal) normalized resistance ( ? ) r wb r wa v dd = +3v to +5v -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 code (decimal) potentiometer inl error (lsb) t a = -40c to +85c refer to figure 2-25 -10 0 10 20 30 40 50 60 70 0 32 64 96 128 160 192 224 256 code (decimal) potentiometer mode tempco (ppm / c) t a = -40c to +85c v a = 3v 0 2 4 6 8 10 12 14 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) nominal resistance (k ? ) r ab r wb code = 80h mcp41010, mcp42010 (10 k ? potentiometers) 0 10 20 30 40 50 60 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) nominal resistance (k ? ) r ab r wb code = 80h mcp41050, mcp42050 (50 k ? potentiometers ) 0 20 40 60 80 100 120 140 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) nominal resistance (k ? ) mcp41100, mcp42100 (100 k ? potentiometers) r ab r wb code = 80h
mcp41xxx/42xxx ds11195c-page 8 ? 2003 microchip technology inc. note: unless otherwise indicated, curve represents 10 k ? , 50 k ? and 100 k ? devices, v dd = 5v, v ss = 0v, t a = +25c, v b = 0v. figure 2-7: rheostat inl error vs. code. figure 2-8: rheostat mode tempco vs. code. figure 2-9: static current vs. temperature. figure 2-10: active supply current vs. temperature. figure 2-11: active supply current vs. clock frequency. figure 2-12: reset & shutdown pins current vs. voltage. -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 code (decimal) rheostat inl error (lsb) t a = +25c t a = +85c t a = -40c refer to figure 2-27 0 500 1000 1500 2000 2500 3000 0 32 64 96 128 160 192 224 256 code (decimal) rheostat mode tempco (ppm / c) t a = -40c to +85c, v a = no connect, r wb measured 1 10 100 1000 -40 -25 -10 5 20 35 50 65 80 95 11 0 12 5 temperature (c) static current (na) 30 80 130 180 230 280 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) active supply current (a) v dd = 5v v dd = 3v f clk = 3 mhz code = ffh 0 100 200 300 400 500 600 700 800 900 1000 clock frequency (hz) active supply current (ma) a - v dd = 5.5v, code = aah b - v dd = 3.3v, code = aah c - v dd = 5.5v, code = ffh d - v dd = 3.3v, code = ffh a b c d 1k 10k 100k 1m 10m -7 -6 -5 -4 -3 -2 -1 0 1 0246 rs & shdn pin voltage (v) rs & shdn sink current (ma) v dd = 5.5v
? 2003 microchip technology inc. ds11195c-page 9 mcp41xxx/42xxx note: unless otherwise indicated, curve represents 10 k ? , 50 k ? and 100 k ? devices, v dd = 5v, v ss = 0v, t a = +25c, v b = 0v. figure 2-13: 10 k ? device wiper resistance histogram. figure 2-14: 50 k ? , 100 k ? device wiper resistance histogram. figure 2-15: one position settling time. figure 2-16: full-scale settling time. figure 2-17: digital feed through vs. time. figure 2-18: gain vs. frequency for 10 k ? potentiometer. 0 20 40 60 80 100 120 140 160 180 47 48 49 50 51 52 53 54 55 56 57 58 59 wiper resistance ( ? ) number of occurrences mcp41010,mcp42010 code = 00h, sample size = 400 0 20 40 60 80 100 120 140 115 117 119 121 123 125 127 129 131 133 wiper resistance ( ? ) number of occurrences mcp41050, mcp41100, mcp42050, mcp42100 code = 00h, sample size = 796 v out code = 7fh code = 80h cs c l = 17 pf v out 00h ffh cs c l = 27 pf c l = 27 pf code = 80h v out cs -60 -54 -48 -42 -36 -30 -24 -18 -12 -6 0 6 frequency (hz) gain (db) c l = 30pf, refer to figure 2-29 mcp41010, mcp42010 (10k ? potentiometers) code = ffh code = 80h code = 40h code = 20h code = 10h code = 08h code = 04h code = 02h code = 01h 100 1k 10k 100k 1m 10 m
mcp41xxx/42xxx ds11195c-page 10 ? 2003 microchip technology inc. note: unless otherwise indicated, curve represents 10 k ? , 50 k ? and 100 k ? devices, v dd = 5v, v ss = 0v, t a = +25c, v b = 0v. figure 2-19: gain vs. frequency for 50k ? potentiometer. figure 2-20: gain vs. frequency for 100k ? potentiometer. figure 2-21: -3 db bandwidths. figure 2-22: power supply rejection ratio vs. frequency. figure 2-23: 10 k ? wiper resistance vs. voltage. figure 2-24: 50 k ? & 100 k ? wiper resistance vs. voltage. -60 -54 -48 -42 -36 -30 -24 -18 -12 -6 0 6 frequency (hz) gain (db) c l = 30pf, refer to figure 2-29 mcp41050, mcp42050 (50k ? potentiometers) code = ffh code = 80h code = 40h code = 20h code = 10h code = 08h code = 04h code = 02h code = 01h 100 1k 10k 100k 1m 10m -60 -54 -48 -42 -36 -30 -24 -18 -12 -6 0 6 frequency (hz) gain (db) c l = 30pf, refer to figure 2-29 mcp41100, mcp42100 (100k ? potentiometers) code = ffh code = 80h code = 40h code = 20h code = 10h code = 08h code = 04h code = 02h code = 01h 100 1k 10k 100k 1m -36 -30 -24 -18 -12 -6 0 frequency (hz) gain (db) 279 khz 145 khz 1.06 mhz 10 k ? 50 k ? 100 k ? c l = 30 pf, code = 80h refer to figure 2-29 1k 10k 100k 1m 10 m 0 5 10 15 20 25 30 35 40 frequency (hz) psrr (db) 100 k ? potentiometer 50 k ? potentiometer 10 k ? potentiometer v dd = 4.5v to 5.5v, code = 80h, c l = 27 pf, v a = 4v refer to figure 2-28 1k 10k 100k 1m 10 m 0 100 200 300 400 500 600 700 012345 terminal b voltage (v) wiper resistance ( ? ) mcp41010, mcp42010 iw = 1 ma, code = 00h, refer to figure 2-27 v dd = 2.7v v dd = 5v 0 50 100 150 200 250 300 350 400 450 012345 terminal b voltage (v) wiper resistance ( ? ) v dd = 2.7v v dd = 5v code = 00h refer to figure 2-27
? 2003 microchip technology inc. ds11195c-page 11 mcp41xxx/42xxx 2.1 parametric test circuits figure 2-25: potentiometer divider non- linearity error test circuit (dnl, inl). figure 2-26: resistor position non- linearity error test circuit (rheostat operation dnl, inl). figure 2-27: wiper resistance test circuit. figure 2-28: power supply sensitivity test circuit (pss, psrr). figure 2-29: gain vs. frequency test circuit. figure 2-30: capacitance test circuit. v+ a b w v meas * v+ = v dd 1lsb = v+/256 dut * assume infinite input impedance + - a b w dut i w * assume infinite input impedance v meas * no connection + - b dut w + - i sw rsw = 0.1v isw code = 00h 0.1v v ss = 0 to v dd a v+ a b w dut v a v+ = v dd 10% psrr (db) = 20log ? v meas ) ( pss (%/%) = ? v dd ? v meas v dd * assume infinite input impedance v meas * ? v dd + - v in - + +5v v out 2.5v dc offset gnd a b dut w ~ v in - + +5v v out mcp601 2.5v dc offset a b dut ~
mcp41xxx/42xxx ds11195c-page 12 ? 2003 microchip technology inc. 3.0 pin descriptions 3.1 pa0, pa1 potentiometer terminal a connection. 3.2 pb0, pb1 potentiometer terminal b connection. 3.3 pw0, pw1 potentiometer wiper connection. 3.4 chip select (cs ) this is the spi port chip select pin and is used to exe- cute a new command after it has been loaded into the shift register. this pin has a schmitt trigger input. 3.5 serial clock (sck) this is the spi port clock pin and is used to clock-in new register data. data is cl ocked into the si pin on the rising edge of the clock and out the so pin on the falling edge of the clock. this pin is gated to the cs pin (i.e., the device will not draw any more current if the sck pin is toggling when the cs pin is high). this pin has a schmitt trigger input. 3.6 serial data input (si) this is the spi port serial data input pin. the command and data bytes are clocked into the shift register using this pin. this pin is gated to the cs pin (i.e., the device will not draw any more current if the si pin is toggling when the cs pin is high). this pin has a schmitt trigger input. 3.7 serial data output (so) (mcp42xxx devices only) this is the spi port serial data output pin used for daisy-chaining more than one device. data is clocked out of the so pin on the fal ling edge of clock. this is a push-pull output and does not go to a high-impedance state when cs is high. it will drive a logic-low when cs is high. 3.8 reset (rs ) (mcp42xxx devices only) the reset pin will set all potentiometers to mid-scale (code 80h) if this pin is brought low for at least 150 ns. this pin should not be toggled low when the cs pin is low. it is possible to toggle this pin when the shdn pin is low. in order to minimize power consumption, this pin has an active pull-up circuit. the performance of this circuit is shown in figure 2-12. this pin will draw negli- gible current at logic level ? 0 ? and logic level ? 1 ?. do not leave this pin floating. 3.9 shutdown (shdn) (mcp42xxx devices only) the shutdown pin has a schmitt trigger input. pulling this pin low will put the device in a power-saving mode where a terminal is opened and the b and w terminals are connected for all potentiometers. this pin should not be toggled low when the cs pin is low. in order to minimize power consumption, this pin has an active pull-up circuit. the performance of this circuit is shown in figure 2-12. this pin will draw negligible current at logic level ? 0 ? and logic level ? 1 ?. do not leave this pin floating. table 3-1: mcp41xxx pins table 3-2: mcp42xxx pins pin # name function 1cs chip select 2 sck serial clock 3 si serial data input 4v ss ground 5 pa0 terminal a connection for pot 0 6 pw0 wiper connection for pot 0 7 pb0 terminal b connection for pot 0 8v dd power pin # name function 1cs chip select 2 sck serial clock 3 si serial data input 4v ss ground 5 pb1 terminal b connection for pot 1 6 pw1 wiper connection for pot 1 7 pa1 terminal a connection for pot 1 8 pa0 terminal a connection for pot 0 9 pw0 wiper connection for pot 0 10 pb0 terminal b connection for pot 0 11 rs reset input 12 shdn shutdown input 13 so data out for daisy-chaining 14 v dd power
? 2003 microchip technology inc. ds11195c-page 13 mcp41xxx/42xxx 4.0 applications information the mcp41xxx/42xxx devic es are 256 position single and dual digital potentiometers that can be used in place of standard mechanical pots. resistance val- ues of 10 k ? , 50 k ? and 100 k ? are available. as shown in figure 4-1, each potentiometer is made up of a variable resistor and an 8-bit (256 position) data reg- ister that determines the wip er position. there is a nominal wiper resistance of 52 ? for the 10 k ? version, 125 ? for the 50 k ? and 100 k ? versions. for the dual devices, the channel-to-channel matching variation is less than 1%. the resistance between the wiper and either of the resistor endpoints varies linearly according to the value stored in the data register. code 00h effectively connects the wi per to the b terminal. at power-up, all data registers will automatically be loaded with the mid-scale value (80h). the serial interface pro- vides the means for loading data into the shift register, which is then transferred to the data registers. the serial interface also provides the means to place indi- vidual potentiometers in th e shutdown mode for maxi- mum power savings. the shdn pin can also be used to put all potentiometers in shutdown mode and the rs pin is provided to set all potentiometers to mid-scale (80h). figure 4-1: block diagram showing the mcp42xxx dual di gital potentiometer. da ta register 0 and data register 1 are 8-bit registers allowing 256 posit ions for each wiper. standard spi pins are used with the addition of the shutdown (shdn ) and reset (rs ) pins. as shown, reset affects the data register and wipers, bringing them to mid-scale. shutdown disconnects the a terminal and connects the wiper to b, without changing the state of the data registers. when laying out the circuit for your digital potentiome- ter, bypass capacitors should be used. these capaci- tors should be placed as close as possible to the device pin. a bypass capacitor va lue of 0.1 f is recom- mended. digital and analog traces should be separated as much as possible on the board, with no traces run- ning underneath the device or the bypass capacitor. extra precautions should be taken to keep traces with high-frequency signals (such as clock lines) as far as possible from analog traces . use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. rdac1 sck so si decode logic 16-bit shift register pa0 pb0 pw0 rdac2 data register 1 cs rs shdn d7 d0 data register 0 d7 d0 d7 d0 pa1 pb1 pw1 v dd a b w v dd mcp4xxxx c to application circuit 0.1 uf 0.1 uf data lines
mcp41xxx/42xxx ds11195c-page 14 ? 2003 microchip technology inc. 4.1 modes of operation digital potentiometer applications can be divided into two categories: rheostat mode and potentiometer, or voltage divider, mode. 4.1.1 rheostat mode in the rheostat mode, the pot entiometer is used as a two-terminal resistive element. the unused terminal should be tied to the wiper, as shown in figure 4-2. note that reversing the polarity of the a and b terminals will not affect operation. figure 4-2: two-terminal or rheostat configuration for the digital potentiometer. acting as a resistive element in the circuit, resistance is controlled by changing the wiper setting. using the device in this mode allows control of the total resistance between the two nodes. the total measured resistance would be the least at code 00h, where the wiper is tied to the b terminal. the resistance at this code is equal to the wiper resistance, typically 52 ? for the 10 k ? mcp4x010 devices, 125 ? for the 50 k ? (mcp4x050), and 100 k ? (mcp4x100) devices. for the 10 k ? device, the lsb size would be 39.0625 ? (assuming 10 k ? total resistance). the resistance would then increase with this lsb size until the total measured resistance at code ffh would be 9985.94 ? . the wiper will never directly connect to the a terminal of the resistor stack. in the 00h state, the total resistance is the wiper resis- tance. to avoid damage to the internal wiper circuitry in this configuration, care should be taken to ensure the current flow never exceeds 1 ma. for dual devices, the variation of channel-to-channel matching of the total resistance from a to b is less than 1%. the device-to-device matching, however, can vary up to 30%. in the rheostat mode, the resistance has a positive temperature coefficient. the change in wiper- to-end terminal resistance ov er temperature is shown in figure 2-8. the most variation over temperature will occur in the first 6% of codes (code 00h to 0fh) due to the wiper resistance coefficient affecting the total resis- tance. the remaining codes are dominated by the total resistance tempco r ab , typically 800 ppm/c. 4.1.2 potentiometer mode in the potentiometer mode, all three terminals of the device are tied to different nodes in the circuit. this allows the potentiometer to output a voltage propor- tional to the input voltage. this mode is sometimes called voltage divider mode. the potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in figure 4-3. note that reversing the polarity of the a and b terminals will not affect operation. figure 4-3: three terminal or voltage divider mode. in this configuration, the ratio of the internal resistance defines the temperature coefficient of the device. the resistor matching of the r wb resistor to the r ab resistor performs with a typical te mperature coefficient of 1 ppm/c (measured at code 80h). at lower codes, the wiper resistance temperature coefficient will dominate. figure 2-3 shows the effect of the wiper. above the lower codes, this figure shows that 70% of the states will typically have a temperature coefficient of less than 5 ppm/c. 30% of the stat es will typically have a ppm/c of less than 1. a b w mcp4xxxx resistor a b w mcp4xxxx v 1 v 2
? 2003 microchip technology inc. ds11195c-page 15 mcp41xxx/42xxx 4.2 typical applications 4.2.1 programmabl e single-ended amplifiers potentiometers are often used to adjust system refer- ence levels or gain. programmable gain circuits using digital potentiometers can be realized in a number of different ways. an example of a single-supply, inverting gain amplifier is shown in figure 4-4. due to the high input impedance of the amplifier, the wiper resistance is not included in the transfe r function. for a single-sup- ply, non-inverting gain configuration, the circuit in figure 4-5 can be used. . figure 4-4: single-supply, programmable, inverting gain amplifier using a digital potentiometer. figure 4-5: single-supply, programmable, non-inverting gain amplifier. in order for these circuits to work properly, care must be taken in a few areas. for linear operation, the analog input and output signals must be in the range of v ss to v dd for the potentiometer and input and output rails of the op-amp. the circuit in figure 4-4 requires a virtual ground or reference input to the non-inverting input of the amplifier. refer to application note 682, ?using single-supply operational amplifiers in embedded systems? (ds00682), for more details. at power-up or reset (rs) , the resistance is set to mid-scale, with r a and r b matching. based on the transfer function for the circuit, the gain is -1 v/v. as the code is increased and the wiper moves towards the a terminal, the gain increases. conversely, when the wiper is moved towards the b terminal, the gain decreases. figure 4-6 shows this relationship. no tice the pseudo-logarithmic gain around decimal code 128. as the wiper approaches either terminal, the step size in the gain calculation increases dramatically. due to the mismatched ratio of r a and r b at the extreme high and low codes, small increments in wiper position can dramatically affect the gain. as shown in figure 4-3, recommended gains lie between 0.1 and 10 v/v. figure 4-6: gain vs. code for inverting and differential amplifier circuits. 4.2.2 programmable differential amplifier an example of a differential input amplifier using digital potentiometers is shown in figure 4-7. for the transfer function to hold, both pots must be programmed to the same code. the resistor-matching from channel-to- channel within a dual device can be used as an advan- tage in this circuit. this circuit will also show stable operation over temperature due to the low potentiome- ter temperature coefficient. figure 4-6 also shows the relationship between gain and code for this circuit. as the wiper approaches either terminal, the step size in the gain calculation increases dramatically. this circuit is recommended for gains between 0.1 and 10 v/v. mcp606 v in v ss -in +in v out b a w mcp41010 where: v ref + - v dd v out v in r b r a ------- ?? ?? v ref 1 r b r a ------- + ?? ?? + ? = r a r ab 256 d n ? () 256 --------------------------------------- = r b r ab d n 256 ------------------ = r ab total resistance of pot = d n wiper setting ford n 0 to 255 = = mcp606 v in v ss v dd +in -in v out rb ra w mcp41010 + - where: r a r ab 256 d n ? () 256 --------------------------------------- = r b r ab d n 256 ------------------ = r ab total resistance of pot = d n wiper setting ford n 0 to 255 = = v out v in 1 r b r a ------- + ?? ?? = 0.1 1 10 0 64 128 192 256 decimal code (0-255) absolute gain (v/v)
mcp41xxx/42xxx ds11195c-page 16 ? 2003 microchip technology inc. figure 4-7: single supply programmable differential amplifier using digital potentiometers. 4.2.3 programmabl e offset trim for applications requiring only a programmable voltage reference, the circuit in figure 4-8 can be used. this circuit shows the device used in the potentiometer mode along with two resistors and a buffered output. this creates a circuit with a linear relationship between voltage-out and programmed code. resistors r 1 and r 2 can be used to increase or decrease the output volt- age step size. the potentiometer in this mode is stable over temperature. the oper ation of this circuit over temperature is shown in figure 2-3. the worst perfor- mance over temperature will occur at the lower codes due to the dominating wiper resistance. r 1 and r 2 can also be used to affect the boundary voltages, thereby eliminating the use of these lower codes. figure 4-8: by changing the values of r 1 and r 2 , the voltage output resolution of this programmable voltage reference circuit is affected. 4.3 calculating resistances when programming the digital potentiometer settings, the following equations can be used to calculate the resistances. programming code 00h effectively brings the wiper to the b terminal, leaving only the wiper resis- tance. programming higher codes will bring the wiper closer to the a terminal of the potentiometer. the equa- tions in figure 4-9 can be used to calculate the terminal resistances. figure 4-10 shows an example calculation using a 10 k ? potentiometer. figure 4-9: potentiometer resistances are a function of code. it should be noted that, when using these equations for most feedback amplifier circuits (see figure 4-4 and figure 4-5), the wiper resistance can be omitted due to the high impedance input of the amplifier. figure 4-10: example resistance calculations. mcp601 v b v ss v dd -in +in v out ab a b (sig -) mcp42010 mcp42010 1/2 1/2 v ref note: potentiometer values must be equal + - where: r a r ab 256 d n ? () 256 --------------------------------------- = r b r ab d n 256 ------------------ = r ab total resistance of pot = d n wiper setting ford n 0 to 255 = = v out v a v b ? () r b r a ------- = v a (sig +) mcp606 out v ss v dd -in +in v dd v ss r 1 r 2 b a mcp41010 0.1 uf + - pa pb pw where: pa is the a terminal pb is the b terminal pw is the wiper terminal r wa is resistance between terminal a and wiper r wb is resistance between terminal b and wiper r ab is overall resistance for pot (10 k ? , 50 k ? or 100 k ? ) r w is wiper resistance d n is 8-bit value in data register for pot number n r wa d n () r ab () 256 d n ? () 256 ------------------------------------------- - r w + = r wb d n () r ab () d n () 256 --------------------------- - r w + = example: code = c0h = 192d r = 10 k ? note: all values shown are typical and actual results will vary . pa pb pw 10 k ? r wa d n () r ab () 256 d n ? () 256 ------------------------------------------- - r w + = r wb c0h () 10k ? () 192 () 256 ---------------------------------- - 52 ? + = r wa c0h () 10k ? () 256 192 ? () 256 -------------------------------------------------- - 52 ? + = r wa c0h () 2552 ? = r wb d n () r ab () d n () 256 --------------------------- - r w + = r wb c0h () 7552 ? =
? 2003 microchip technology inc. ds11195c-page 17 mcp41xxx/42xxx 5.0 serial interface communications from the controller to the mcp41xxx/42xxx digital pote ntiometers is accom- plished using the spi serial interface. this interface allows three commands: 1. write a new value to the potentiometer data register(s). 2. cause a channel to enter low power shutdown mode. 3. nop (no operation) command. executing any command is accomplished by setting cs low and then clocking-in a command byte followed by a data byte into the 16-bit shift register. the com- mand is executed when cs is raised. data is clocked- in on the rising edge of clock and out the so pin on the falling edge of the clock (see figure 5-1). the device will track the number of clocks (rising edges) while cs is low and will abort all commands if the number of clocks is not a multiple of 16. 5.1 command byte the first byte sent is always the command byte, fol- lowed by the data byte. the command byte contains two command select bits and two potentiometer select bits. unused bits are ?don?t care? bits. the command select bits are summarized in figure 5-2. the com- mand select bits c1 and c0 (bits 4:5) of the command byte determine which command will be executed. if the command bits are both 0 ?s or 1 ?s, then a nop com- mand will be executed once all 16 bits have been loaded. this command is useful when using the daisy- chain configuration. when the command bits are 0 , 1 , a write command will be execut ed with the 8 bits sent in the data byte. the data will be written to the potentiom- eter(s) determined by the potentiometer select bits. if the command bits are 1 , 0 , then a shutdown command will be executed on the potentiometers determined by the potentiometer select bits. for the mcp42xxx devices, the potentiometer select bits p1 and p0 (bits 0:1) determine which potentiome- ters are to be acted upon by the command. a corre- sponding ? 1 ? in the position signifies that the command for that potentiometer will get executed, while a ? 0 ? sig- nifies that the command will not effect that potentiometer (see figure 5-2). 5.2 writing data into data registers when new data is written into one or more of the poten- tiometer data registers, t he write command is followed by the data byte for the new value. the command select bits c1, c0 are set to 0 , 1 . the potentiometer selection bits p1 and p0 allow new values to be written to potentiometer 0, potentiometer 1 (or both) with a sin- gle command. a ? 1 ? for either p1 or p0 will cause the data to be written to the respective data register and a ? 0 ? for p1 or p0 will cause no change. see figure 5-2 for the command format summary. 5.3 using the shutdown command the shutdown command allows the user to put the application circuit into a power-saving mode. in this mode, the a terminal is open-circuited and the b and w terminals are shorted toget her. the command select bits c1, c0 are set to 1 , 0 . the potentiometer selection bits p1 and p0 allow each potentiometer to be shut- down independently. if either p1 or p0 are high, the respective potentiometer will enter shutdown mode. a ? 0 ? for p1 or p0 will have no effect. the eight data bits following the command byte still need to be transmitted for the shutdown command, but they are ?don?t care? bits. see figure 5-2 for command format summary. once a particular potentiometer has entered the shut- down mode, it will remain in this mode until: ? a new value is written to the potentiometer data register, provided that the shdn pin is high. the device will remain in the shutdown mode until the rising edge of the cs is detected, at which time the device will come out of shutdown mode and the new value will be written to the data regis- ter(s). if the shdn pin is low when the new value is received, the registers will still be set to the new value, but the device will remain in shutdown mode. this scenario assumes that a valid com- mand was received. if an invalid command was received, the command will be ignored and the device will remain in the shutdown mode. it is also possible to use the hardware shutdown pin and reset pin to remove a device from software shut- down. to do this, a low pulse on the chip select line must first be sent. for multip le devices, sharing a single shdn or reset line allows you to pick an individual device on that chain to remove from software shutdown mode. see figure 1-3 for timing. with a preceding chip select pulse, either of these situations will also remove a device from software shutdown: ? a falling edge is seen on the rs pin and held low for at least 150 ns, provided that the shdn pin is high. if the shdn pin is low, the registers will still be set to mid-scale, but the device will remain in shutdown mode. this condition assumes that cs is high, as bringing the rs pin low while cs is low is an invalid state and results are indeterminate. ? a rising edge on the shdn pin is seen after being low for at least 100 ns, provided that the cs pin is high. toggling the shdn pin low while cs is low is an invalid state and results are indeterminate. ? the device is powered-down and back up. note: the hardware shdn pin will always put the device in shutdown regardless of whether a potentiometer has already been put in the shutdown mode using the software command.
mcp41xxx/42xxx ds11195c-page 18 ? 2003 microchip technology inc. figure 5-1: timing diagram for writing instructions or data to a dig ital potentiometer. figure 5-2: command byte format. so ? si sck cs ? 2345678 910 1 new register data d7 d6 d5 d4 d3 d2 d1 d0 p1* p0 11 12 13 14 15 16 x c1 c0 x x x channel select bits data registers are loaded on rising edge of cs. shift first 16 bits shifted out will always be zeros don?t care bits command bits don?t care bits ? there must always be multiples of 16 cloc ks while cs is low or commands will abort. ? the serial data out pin (so) is only available on the mcp42xxx device. * p1 is a ?don?t care? bit for the mcp41xxx. command byte data byte x register is loaded with zeros at this time. data is always latched in on the rising edge data is always clocked out of the so pin after the so pin will always drive low when cs goes high. of sck. falling edge of sck. p1* p0 potentiometer selections 0 0 dummy code: neither potentiometer affected. 0 1 command executed on potentiometer 0. 1 0 command executed on potentiometer 1. 1 1 command executed on both potentiometers. p0 p1* xx x xc1c0 command byte c1 c0 command command summary 0 0 none no command will be executed. 0 1 write data write the data contained in data byte to the potentiometer(s) determined by the potenti- ometer selection bits. 1 0 shutdown potentiometer(s) determined by potentiome- ter selection bits will enter shutdown mode. data bits for this command are ?don?t cares?. 1 1 none no command will be executed. command selection bits potentiometer selection bits
? 2003 microchip technology inc. ds11195c-page 19 mcp41xxx/42xxx 5.4 daisy-chain configuration multiple mcp42xxx devices can be connected in a daisy-chain configuration, as shown in figure 5-4, by connecting the so pin from one device to the si pin on the next device. the data on the so pin is the output of the 16-bit shift register. the daisy-chain configuration allows the system designer to communicate with sev- eral devices without using a separate cs line for each device. the example shows a daisy-chain configura- tion with three devices, although any number of devices (with or without the same resistor values) can be configured this way. while it is not possible to use a mcp41xxx at the beginning or middle of a daisy-chain (because it does not provide the serial data out (so) pin), it is possible to use the device at the end of a chain. as shown in the timing diagram in figure 5-3, data will be clocked-out of the so pin on the falling edge of the clock. the so pin has a cmos push-pull output and will drive low when cs goes high. so will not go to a high-impedance state when cs is held high. when using the daisy-chain configuration, the maxi- mum clock speed possible is reduced to ~5.8 mhz, because of the propagation delay of the data coming out of the so pin. when using the daisy-chain c onfiguration, keep in mind that the shift register of each device is automatically loaded with zeros whenever a command is executed (cs = high). because of this, the first 16 bits that come out of the so pin once the cs line goes low will always be zeros. this means that when the first command is being loaded into a device, it will always shift a nop command into the next device on the chain because the command bits (and all the other bits) will be zeros. this feature makes it nece ssary only to send command and data bytes to the device farthest down the chain that needs a new command. for example, if there were three devices on the chain and it was desired to send a command to the device in the middle, only 32 bytes of data need to be transmitted. the last device on the chain will have a nop loaded from the previous device so no registers will be affected when the cs pin is raised to execute the command. the user must always ensure that multiples of 16 clocks are always provided (while cs is low), as all commands will abort if the number of clocks provided is not a multiple of 16. figure 5-3: timing diagram for daisy-chain configuration. so si sck cs data registers for all devices are loaded on rising edge of cs 2345678910 1 d pp 111213141516 x c xx x first 16 bits shifted out c ddddddd will always be zeros 2345678910 1 d pp 111213141516 x c xx x command and data for device 3 c ddddddd start shifting out after the first 16 clocks d pp xcxx xc ddddddd 2345678910 1 d pp 111213141516 x c xx x c ddddddd d pp xcxx x c ddddddd command byte for device 3 data byte for device 1 command byte for device 1 command byte for device 2 data byte for device 2 data byte for device 3 command and data for device 2 start shifting out after the first 32 clocks ? there must always be multiples of 16 clocks while cs is low or commands will abort. ? the serial data out pin (so) is only available on the mcp42xxx device.
mcp41xxx/42xxx ds11195c-page 20 ? 2003 microchip technology inc. figure 5-4: daisy-chain configuration. microcontroller so cs sck si so cs sck si cs sck si cs sck so device 1 device 2 device 3* if you want to load the following command/data into each part in the chain. device 1 xx10xx11 device 2 xx01xx10 device 3 xx10xx00 example: start by setting cs low and clocking in the command and data that will end up in device 3 (16 clocks). c after 16 clocks, device 2 and device 3 will both have all zeros clocked in from the previous part?s shift register. clock-in the command and data for device 2 (16 more clocks). the data that was pre- viously loaded gets shifted to the next device on the chain. d after 32 clocks , device 2 has the data previously loaded into device 1 and device 3 gets 16 more zeros. clock-in the data for device 1 (16 more clocks). the data that was previously loaded into device 1 gets shifted into device 2 and device 3 contains the first byte loaded. raise the cs line to execute the com- mands for all 3 devices at the same time. e after 48 clocks, all 3 devices have the proper command/ data loaded into their shift registers. * last device on a daisy-chain may be a single channel mcp41xxx device. 11001100 11110000 10101010 device 1 xx10xx00 device 2 00000000 device 3 00000000 10101010 00000000 00000000 device 1 xx01xx10 device 2 xx10xx00 device 3 00000000 11110000 10101010 00000000 device 1 xx10xx11 device 2 xx01xx10 device 3 xx10xx00 11001100 11110000 10101010
? 2003 microchip technology inc. ds11195c-page 21 mcp41xxx/42xxx 5.5 reset (rs ) pin operation the reset pin (rs ) will automatically set all potentiom- eter data latches to mid-scale (code 80h) when pulled low (provided that the pin is held low at least 150 ns and cs is high). the reset will execute regardless of the position of the sck, shdn and si pins. it is possi- ble to toggle rs low and back high while shdn is low. in this case, the potentiometer registers will reset to mid-scale, but the potentiometer will remain in shutdown mode until the shdn pin is raised. 5.6 shutdown (shdn ) pin operation when held low, the shutdown pin causes the applica- tion circuit to go into a power-saving mode by open-cir- cuiting the a terminal and shorting the b and w terminals for all potentiometers. data register contents are not affected by entering shutdown mode (i.e., when the shdn pin is raised, the dat a register contents are the same as before the shutdown mode was entered). while in shutdown mode, it is still possible to clock in new values for the data registers, as well as toggling the rs pin to cause all data registers to go to mid-scale. the new values will take affect when the shdn pin is raised. if the device is powered-up with the shdn pin held low, it will power-up in the shut down mode with the data reg- isters set to mid-scale. 5.7 power-up considerations when the device is powered on, the data registers will be set to mid-scale (80h). a power-on reset circuit is utilized to ensure that the device powers up in this known state. note: bringing the rs pin low while the cs pin is low constitutes an invalid operating state and will result in indeterminate results when rs and/or cs are brought high. note: bringing the shdn pin low while the cs pin is low constitutes an invalid operating state and will result in indeterminate results when shdn and/or cs are brought high. table 5-1: truth table for logic inputs sck cs rs shdn action x ? h h communication is initiated with device. device comes out of standby mode. l l h h no action. device is waiting for data to be clocked into shift register or cs to go high to execute command. | l h x shift one bit into shift register. the shift register can be loaded while the shdn pin is low. ? l h x shift one bit out of shift register on the so pin. the so pin is active while the shdn pin is low. x | h h based on command bits, either load data from shift register into data latches or execute shut- down command. neither com- mand executed unless multiples of 16 clocks have been entered while cs is low. so pin goes to a logic low. x h h h static operation. x h ? h all data registers set and latched to code 80h. x h ? l all data registers set and latched to code 80h. device is in hardware shutdown mode and will remain in this mode. x h h ? all potentiometers put into hardware shutdown mode; terminal a is open and w is shorted to b. x h h | all potentiometers exit hard- ware shutdown mode. potenti- ometers will also exit software shutdown mode if this rising edge occurs after a low pulse on cs . contents of data latches are restored.
mcp41xxx/42xxx ds11195c-page 22 ? 2003 microchip technology inc. 5.8 using the mcp41xxx/42xxx in spi mode 1,1 it is possible to operate t he devices in spi modes 0,0 and 1,1. the only difference between these two modes is that, when using mode 1,1, the clock idles in the high state, while in mode 0,0, th e clock idles in the low state. in both modes, data is clocked into the devices on the rising edge of sck and data is clocked out the so pin once the falling edge of sc k. operations using mode 0,0 are shown in figure 5-1. the example in figure 5-5 shows mode 1,1. figure 5-5: timing diagram for spi mode 1,1 operation. so? si sck cs? 2345678 910 1 new register data d7 d6 d5 d4 d3 d2 d1 d0 p1* p0 11 12 13 14 15 16 x c1 c0 x x x channel select bits data registers are loaded on rising edge of cs. shift first 16 bits shifted out will always be zeros don?t care bits command bits don?t care bits ? there must always be multiples of 16 clocks while cs is low or commands will abort. ? the serial data out pin (so) is only available on the mcp42xxx device. command byte data byte x register is loaded with zeros at this time. data is always latched in on the rising edge of sck. data is always clocked out the so pin after the falling edge of sck. so pin will always drive low when cs goes high.
? 2003 microchip technology inc. ds11195c-page 23 mcp41xxx/42xxx 6.0 packaging information 6.1 package marking information legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part numbe r cannot be marked on one line, it will be carried over to the next line thus limit ing the number of available characters for customer specific information. * standard marking consists of microchip part number , year code, week code, facility code, mask rev#, and assembly code. xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn mcp41010 i/p256 0313 mcp41050 i/sn0313 256 14-lead pdip (300 mil) example: 14-lead soic (150 mil) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxxx yywwnnn mcp42010 i/p 0313256 xxxxxxxxxxx 42050isl 0313256 xxxxxxxxxxx xxxxxxxx nnn yyww 14-lead tssop (4.4mm) * example: 42100i 256 0313
mcp41xxx/42xxx ds11195c-page 24 ? 2003 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 * controlling parameter notes: dimensions d and e1 do not include mold flash or protru sions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
? 2003 microchip technology inc. ds11195c-page 25 mcp41xxx/42xxx 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protru sions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
mcp41xxx/42xxx ds11195c-page 26 ? 2003 microchip technology inc. 14-lead plastic dual in-line (p) ? 300 mil (pdip) e1 n d 1 2 eb e c a a1 b b1 l a2 p units inches* millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 5 10 15 5 10 15 mold draft angle bottom * controlling parameter notes: dimensions d and e1 do not include mold flash or prot rusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-005 significant characteristic
? 2003 microchip technology inc. ds11195c-page 27 mcp41xxx/42xxx 14-lead plastic small outline (sl) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or prot rusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-065 significant characteristic
mcp41xxx/42xxx ds11195c-page 28 ? 2003 microchip technology inc. 14-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 8 4 0 8 4 0 foot angle 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters* inches units l c 2 1 d n b p e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or prot rusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-087 significant characteristic
? 2003 microchip technology inc. ds11195c-page 29 mcp41xxx/42xxx product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, pleas e contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (i nclude literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device device: mcp41010: single digital potentiometer (10 k ? ) mcp41010t: single digital potentiometer (10 k ? ) (tape and reel) mcp41050: single digital potentiometer (50 k ? ) (tape and reel) mcp41050t: single digital potentiometer (50 k ? ) mcp41100: single digital potentiometer (100 k ? ) (tape and reel) mcp41100t: single digital potentiometer (100 k ? ) mcp42010: dual digital potentiometer (10 k ? ) mcp42010t: dual digital potentiometer (10 k ? ) (tape and reel) mcp42050: dual digital potentiometer (50 k ? ) mcp42050t: dual digital potentiometer (50 k ? ) (tape and reel) mcp42100: dual digital potentiometer (100 k ? ) mcp42100t: dual digital potentiometer (100 k ? ) (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c package: p = plastic dip (300 mil body), 8-lead, 14-lead sn = plastic soic (150 mil body), 8-lead sl = plastic soic (150 mil body), 14-lead st = tssop (4.4mm body), 14-lead examples: a) mcp41010-i/sn: i-temp., 8ld soic pkg. b) mcp41010-e/p: e-temp., 8ld pdip pkg. c) mcp41010t-i/sn: tape and reel, i-temp., 8ld soic pkg. d) mcp41050-e/sn: e-temp., 8ld soic pkg. e) mcp41050-i/p: i-temp., 8ld pdip pkg. f) mcp41050-e/sn: e-temp., 8ld soic pkg. g) mcp41100-i/sn: i-temp., 8ld soic package. h) mcp41100-e/p: e-temp., 8ld pdip pkg. i) mcp41100t-i/sn: i-temp., 8ld soic pkg. a) mcp42010-e/p: e-temp., 14ld pdip pkg. b) mcp42010-i/sl: i-temp., 14ld soic pkg. c) mcp42010-e/st: e-temp., 14ld tssop pkg. d) mcp42010t-i/st: tape and reel, i-temp., 14ld tssop pkg. e) mcp42050-e/p: e-temp., 14ld pdip pkg. f) mcp42050t-i/sl: tape and reel, i-temp., 14ld soic pkg. g) mcp42050-e/sl: e-temp., 14ld soic pkg. h) mcp42050-i/st: i-temp., 14ld tssop pkg. i) mcp42050t-i/sl: tape and reel, i-temp., 14ld soic pkg. j) mcp42050t-i/st: tape and reel, i-temp., 14ld tssop pkg. k) mcp42100-e/p: e-temp., 14ld pdip pkg. l) mcp42100-i/sl: i-temp., 14ld soic pkg. m) mcp42100-e/st: e-temp., 14ld tssop pkg. n) mcp42100t-i/sl: tape and reel, i-temp., 14ld soic pkg. o) mcp42100t-i/st: tape and reel, i-temp., 14ld tssop pkg.
mcp41xxx/42xxx ds11195c-page 30 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds11195c-page 31 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meet s with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or othe rwise, under any intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of microc hip technology incorporated in the u.s.a. accuron, application maestr o, dspicdem, dspicdem.net, economonitor, fansense, flexrom, fuzzylab, in- circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, picc, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smarttel and total endurance are trademarks of microchip te chnology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the s pecification contained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating spec ifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer ca n guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly ev olving. we at microchip are committed to conti nuously improving the code protection features of our products. attempts to break microchip?s code protection featur e may be a violation of the digi tal millennium copyright act. if such acts allow unauthorized access to your software or other copyright ed work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
ds11195c-page 32 ? 2003 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 phoenix 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 san jose 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building no. 2 fengxiangnan road, ronggui town shunde city, guangdong 528303, china tel: 86-765-8395507 fax: 86-765-8395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands p. a. de biesbosch 14 nl-5152 sc drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 07/28/03 w orldwide s ales and s ervice

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